High output voltage swing class AB operational amplifier output stage

ABSTRACT

An output stage ( 10 ) is provided having transistors of the same polarity type, which function to amplify the input signal at a wide range of frequencies, with low power consumption and low crossover distortion. By biasing the output transistors to remain on during both the positive and negative voltage swing of the input signal, low power consumption as well as low output crossover distortion is achieved. A high efficiency, low crossover distortion, current amplifier circuit for amplifying an input signal (V IN ) in accordance with this present invention includes an output driver ( 12 ), a current source (I S1 ) and a translinear loop circuit ( 14 ). The output driver ( 12 ) includes a sourcing circuit (Q 6 ). The current source (I S1 ), connected to the output driver ( 12 ), provides bias current to the sourcing circuit. The translinear loop circuit ( 14 ), connected to the output driver ( 12 ), receives the input signal (V IN ). The translinear loop ( 14 ) includes a sinking circuit (Q 7 ), such that the translinear loop circuit ( 14 ) is responsive to the a sinking current of the sinking circuit and operable to provide a bias current signal proportional to the sinking current.

This application claims priority under 35 USC § 119(e)(1) of provisional application No. 60/142,494, filed Jul. 6, 1999.

FIELD OF THE INVENTION

This invention relates generally to the field of operational amplifiers; and, in particular, to an amplifier having minimal zero crossover distortion and quiescent current requirements.

BACKGROUND OF THE INVENTION

Well known in monolithic integrated circuit design, the design of bias circuitry internal to the chip is essential since it determines the internal voltage and current levels over all operating conditions of the integrated circuit as well as over all manufacturing process variations. The industry trend for electronic systems encompassing operational amplifiers is evolving toward lower operating voltages supplied from battery sources. Thus, amplifiers are used in applications requiring low voltage single supply operations in addition to traditionally desired operational amplifier properties such as high input impedance, low input offset voltage, low noise, high bandwidth, high speed and sufficient output drive capabilities.

The operational amplifier consists of at least two stages: an input amplifier stage and an output stage. The input amplifier stage has the task of deriving the difference between the two inputs. The primary purpose of the output stage is voltage amplification. The output stage optionally includes a current boosting scheme which increases the amplifier's load capacity. Conventionally, amplifier output stages have used techniques involving combinations of transistors including npn, pnp and metal oxide semiconductor field effect transistors to satisfy many performance specifications, such as low crossover distortion, high gain factor, large output voltage swings including rail to rail performance, excellent phase and gain margins, low output impedance and symmetrical source and sink capabilities. A well-designed output stage should achieve these performance specifications while consuming low quiescent power and not limiting the frequency response of the amplifier.

During operation, an output stage consumes current from a power supply. A portion of this current, known as the quiescent current, is used to bias the internal circuitry of z; the output stage. The quiescent current is the current required to bias all transistors on when the input is shorted to ground. The purpose of the quiescent current is to provide sufficient base current for the amplifier's output transistors and current to maintain the amplifier's critical circuitry “on.” Low quiescent current is desirable because it reduces power consumption when the amplifier is operating at a light load, or with no load at all. The active components of an all NPN Class AB amplifier include two NPN transistor, wherein the emitter of the first transistor is connected to the collector of the second transistor. The first NPN transistor amplifies the input signal during the positive swing of the signal, and the second NPN transistor amplifies the input signal in its negative swing. The active components may include diodes, resistors and transistors, with increased bias current for the two transistors to reduce crossover distortion.

Traditional Class AB output stages of an operational amplifier are capable of driving a specified minimum impedance load while possessing a low quiescent current. Traditional Class AB output stage “sink” or “source” a significantly larger current in the presence of low impedance loads. Without a quiescent current large enough to bias all transistors critical to the output stage, these transistors will be “cut off” in an effort to drive a low impedance load. Turning this critical circuitry on again, ready for the next amplifier output transition increases crossover distortion.

Conventional AB class output stages drive a minimum impedance load having a given crossover distortion. Where lower impedance loads exist, higher quiescent current is required within the output stage. Going beyond output stage's specified limits of load results in increasingly considerable crossover distortion.

In conclusion, there are existing designs that minimize crossover distortion of the output stages of an amplifier by allowing the active devices to conduct a small amount of current at the crossover point. Some arrangements use both NPN and PNP output transistors which requires more space and operates slower than an all NPN output transistor arrangement. An arrangement utilizing all PNP transistors also requires more space and operates slower than an all NPN output transistor arrangement. These techniques are limited by the quiescent current; hence, a need exists for an output stage that significantly minimizes crossover distortion using an all NPN output transistor arrangement with no quiescent current requirements.

SUMMARY OF THE INVENTION

The present invention relates to an output stage, having transistors of the same polarity type, which function to amplify the input signal at a wide range of frequencies, with low power consumption and low crossover distortion. By biasing the output transistors to remain on during both the positive and negative voltage swing of the input signal, low power consumption as well as low output crossover distortion is achieved. A high efficiency, low crossover distortion, current amplifier circuit for amplifying an input signal in accordance with this present invention includes an output driver, a transistor, a resistor, a current source and a translinear loop circuit. The output driver includes a sourcing circuit. The current source, connected to the output driver, provides bias current to the sourcing circuit. The value of the resistor determines whether the transistor remains on at all times and should not be set such that reverse bias occurs in the sourcing circuit. This resistor enhances the ratio of transistor emitter area between the transistor and a second transistor of the sourcing circuit. The translinear loop circuit, connected to the output driver, receives the input signal. The translinear loop includes a sinking circuit, such that the translinear loop circuit is responsive to the sinking current signal and operable to provide a bias current signal proportional to the sinking current.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings in which like reference numbers indicate like features and wherein:

FIG. 1 is a schematic of an embodiment of an output stage in accordance with the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 illustrates an output stage 10 in accordance with the present invention. This high efficiency, low crossover distortion, output stage 10 includes a current source I_(S1), an output driver 12, a biasing transistor Q₃, a resistor R₂ and a translinear loop 14. The translinear loop 14 includes transistors Q₁ Q₂, Q₄, Q₅, and Q₇, a resistor R₁, and a second current source I_(S2), Current source I_(S2) not only biases the translinear loop 14 but also increases the speed of this Darlington pair. The output driver 12 comprises sourcing circuit which includes a sixth transistor Q₆. The collector of the first transistor Q₁ is connected to a first power supply rail having a positive biasing potential +V_(CC). An input node V_(IN) is connected to the base of the first transistor Q₁. The first resistor R₁ is connected to the emitter of the first transistor Q₁. The collector and the base of the second transistor Q₂ are connected to resistor R₁. R₁ is optional since it serves primarily to keep the quiescent current low. The emitter of the second transistor Q₂ is connected to a second power supply rail −V_(CC). The first current source I_(S1) is connected to the first power supply rail +V_(CC). The collector and base of the third transistor Q₃ are connected to the first current source I_(S1), The collector of the fourth transistor Q₄ is connected to the emitter of the third transistor Q₃. The base of the fourth transistor Q₄ is connected to the base of the second transistor Q₂. The emitter of the fourth transistor Q₄ is connected to the second power supply rail −V_(CC). The collector of the fifth transistor Q₅ is coupled to the first power supply rail +V_(CC), while the base of the fifth transistor Q₅ is connected to the base of the first transistor Q₁. The second current source I_(S2) is connected between the emitter of the fifth transistor Q₅ and the second power supply rail −V_(CC). The base of the seventh transistor Q₇ is connected to tile second current source I_(S2) and the emitter of the seventh transistor Q₇ is connected to the second power supply rail −V_(CC). Current source I_(S2) biases transistor Q₅ and helps to bias the translinear loop. It helps to keep transistor Q₅ on when the circuit 10 is in sinking mode. Transistors Q₅ and Q₇ form a Darlington pair. The collector of the sixth transistor Q₆ is connected to the first power supply rail +V_(CC). The base of the sixth transistor Q₆ is connected to the collector of the third transistor Q₃. The emitter of the sixth transistor Q₆ is connected to an output node OUT. The second resistor R₂ is connected between the emitter of the third transistor Q₃ and the output node OUT. The collector of the seventh transistor Q₇ is connected to the output node OUT.

Transistors Q₆ and Q₇ are the output transistors of the output stage 10. When the AC input signal applied to input node V_(IN) is in the positive range, or is above the crossover point, the circuit is said to be “sinking current” through the output node OUT. Transistor Q₁ is on, drawing current I₁ from the first power supply rail +V_(CC). Current I₁ of transistor Q₁ flows through resistor R₁ and transistor Q₂. Since transistors Q₂ and Q₄ form a current mirror, current I₂ is equivalent to I₁A_(Q2)/A_(Q4), where A_(Q1) and A_(Q2) are the emitter areas of transistors Q₁ and Q₂. Current I₂ flowing through transistor Q₄ comprises the current that is generated by the current source I_(S1) and the current that flows across resistor R₂ from the output node OUT. The current I₃ of transistor Q₅ is equal to the current from the second current source I_(S2) added to the current I_(base) applied to the base of transistor Q₇, such that transistor Q₇ is biased by the translinear loop formed by transistors Q₁, Q₂, Q₄, Q₅ and Q₇.

The voltage developed across R₂ should not be large enough to reverse bias the base emitter junction of transistor Q₆. A small amount of current generated by the current source I_(S1) is applied to the base of sourcing transistor Q₆. Thus, the output transistor Q₆ remains on when the output transistor Q₇ is sinking current.

More particularly, when AC input signal applied to input node V_(IN) has a positive voltage swing, the voltage applied to the base of transistors Q₁ and Q₅ is positive and thus, the emitter voltage of transistor Q₁ and Q₅ is positive as well. The positive voltage applied to the base of both transistors Q₁ and Q₅ increases the current I₁ and I₃ that flows through each transistor Q₁ and Q₅, respectively. Current I₁, flowing through resistor R₁ and transistor Q₂, increases. Since current I₂ is the mirror of current I₁, current I₂ increases relative to the increase in current I₁. The increase in current I₂ is drawn from the current supplied by the current source I_(S1) and the current through the output node OUT across resistor R₂. As a result, less current is applied to the base of transistor Q₆. Transistor Q₆, however, is left with enough current to keep it on; yet, it does not source any current through the output node OUT.

Transistor Q₅ is more sensitive to changes in the input voltage applied at input node V_(IN) than transistor Q₁. The emitter voltage of transistor Q₅ is applied to the base of transistor Q₇. Since the input voltage V_(IN) increases the base emitter voltage of transistor Q₅ with respect to −V_(CC), a positive voltage is applied to the base of transistor Q₇. As a result, the collector voltage of Q₇ is negative—the output stage 10 is thus sinking current. Due to the increase in current I₃ through transistor Q₅, more current is applied to the base of transistor Q₇. Accordingly, transistor Q₇ sinks more current.

Transistors Q₁, Q₂, Q₄, Q₅, and Q₇ form a translinear loop. The Kirchoff's voltage equation provides that:

Vbe_(Q1)+Vbe_(Q4)=Vbe_(Q5)+Vbe_(Q7), assuming R₁=0  (1)

V_(t)ln(I₁/A_(Q1)I_(S))+V_(t)ln(I₂/A_(Q4)I_(S))=V_(t)ln (I₃/A_(Q5)I_(S))+V_(t)ln (I₄/A_(Q7)I_(S))  (2)

I₄=I_(sink)=(I₁I₂A_(Q5)A_(Q7))/(A_(Q1)A_(Q4)I₃)  (3)

where Vbe_(Q1), Vbe_(Q4), Vbe_(Q5), and Vbe_(Q7) represent the base-emitter voltages of transistors Q₁, Q₄, Q₅, and Q₇, respectively. Areas A_(Q1), A_(Q4), A_(Q5), and A_(Q7) represent the emitter area of each respective transistor. Current I_(S) is the inverse saturation current. Thus, the sinking current I_(sink) is proportional to the boosting current I₂ of transistors Q₃ and Q₄. Since transistors Q₂ and Q₄ form a current mirror, current I₂ is equivalent to I₁A_(Q2)/A_(Q4), where A_(Q1) and A_(Q2) are the emitter areas of transistors Q₁ and Q₂. Thus, the sinking current I_(sink) is proportional to the square of the current provided by the input signal or the current source I_(S1).

The sinking current I_(sink) becomes very large when I₁ and I₂ have unlimited supply current. The power supply generates current I₁. Current I₂ comprises current from the current source I_(S1) and the current being sourced from the output node OUT through resistor R₂. During sinking conditions, the only current drive limitation is determined by the available base current to transistor Q₅ and Q₇. More particularly, this current is represented by Isink/hfe_(Q5)*hfe_(Q7); since:

I₄=I_(B7) hfe_(Q7)

I_(C5)=I_(B5) hfe_(Q5)

I_(sink)=I_(B5) hfe_(Q5) hfe_(Q7)

I_(B5)=I_(sink)/hfe_(Q5) hfe_(Q7)

Thus, there is no significant limiting factor for the current in the output stage sinking current from a given load.

The circuit significantly depreciates crossover distortion in the output signal, by keeping transistors Q₆ and Q₇ on at all times. As the input signal applied to input node V_(IN) approaches the crossover point during either a falling transition, the amount of current I₂ drawn from the current source I_(S1) is reduced. When the input signal applied to input node V_(IN) reaches the crossover point, the amount of current drawn by transistor Q₃ is minimal yet the transistors Q₃ and Q₄ remain biased on. At this stage, virtually no load current is being supplied by the circuit.

When the input voltage applied to input node V_(IN) is at the crosspoint or is negligible, the current I₃ through transistor Q₅ will be approximately equal to current from current source I_(S2). Current I₁ flows through transistors Q₁ and Q₂ and resistor R₁. The current source I_(S1) ‘quiescently’ biases transistors Q₃ and Q₆. Current I₄ is not large enough to sink current from the output load. The base-emitter voltage of transistor Q₇ influences current I₃ which flows through transistor Q₅. The base-emitter voltage of transistor Q₅ is set by the current I₃. Since the bases of transistors Q₁ and Q₅ are coupled together the base-emitter voltage of transistor Q₁ added to the base-emitter voltage of Q₂ is the same as the base-emitter voltage of transistor Q₅ added to the base-emitter voltage of transistor Q₇. Current I₁ is determined by the sum of base-emitter voltages of transistors Q₁ and Q₂. Since transistors Q₂ and Q₄ form a current mirror, current I₂ is equivalent to I₁A_(Q2)/A_(Q4). Resistor R₂ is set such that no current comes through the output node OUT to be added to current I₂. Thus, current I₂ equals the current from current source I_(S1) solely. In summary, at the quiescent point, all transistors are conducting current and are set by the current source I_(S1).

When the input voltage applied to input node V_(IN) swings in the negative direction, the voltage across transistors Q₁ and Q₅ is negative. The negative voltage is applied to the base of transistors Q₁, Q₂, and Q₄. The collector voltage of transistor Q₄, however, is positive. This positive voltage is applied to the emitter of transistor Q₃. As a result, this positive voltage is applied the base and collector of transistor Q₃ and to the base of transistor Q₆. At this point, the amount of current I₂ drawn from the current source I_(S1) decreases. Yet, the amount of current drawn by transistor Q₃ is maximum. A large amount of current from current source I_(S1) is applied to the base of transistor Q₆. At this point, transistor Q₆ conducts current. The circuit is said to be “sourcing current” through the output node OUT to a load connected to the output node OUT.

The dynamic biasing which boosts transistor Q₆ during sourcing mode of the output stage depends upon the amount of current through transistor Q₃ and resistor R₂. If the resistance of resistor R₂ is small enough to make the voltage across it to be zero, then the ratio of the emitter area of transistors Q₃ to Q₆ biases the output transistor Q₆ during the sourcing mode of the output stage. It is the purpose of resistor R₂ to enhance the ratio of transistor's Q₃ and Q₆ emitter area during sourcing mode to provide a larger ratio, such that a small current through transistor Q₃ results in sourcing a large current through transistor Q₆. Using Kirchoff's voltage equation rules, the base-emitter voltage of transistor Q₆ is equal to the voltage across resistor R₂ added to the base-emitter voltage of transistor Q₃.

Since current I₂ decreases, current I₃ decreases and, as a result, the base-emitter voltage of transistor Q₇ decreases. Transistor Q₇, however, remains on. Transistor Q₇ is more likely to remain “on” during sourcing since the translinear loop will tend to keep all transistors operating as long as a small amount of current flows through transistor Q₄. Since the current path to transistor Q₇ is through transistors Q₃ and Q₅, as well as resistor R₂, transistor Q₇ will remain “on” as long as the voltage drop across R₂ is maintained under couple hundred millivolts. In addition, the value of resistor R₂ determines whether Q₃ remains “on.”

Those skilled in the art to which the invention relates will appreciate that various substitutions, modifications and additions can be made to the described embodiments, without departing from the spirit and scope of the invention as defined by the claims. 

What is claimed is:
 1. A high efficiency, low crossover distortion, current amplifier circuit having an input and output node for amplifying an input signal comprising: a first current source for providing bias current to a sourcing circuit coupled to a first power supply rail; an output driver coupled to the first current source and the output node, the output driver including a sourcing circuit; a first transistor having a collector, base and emitter, the base and collector coupled to the current source; a resistor coupled between the emitter of the first transistor and the output node; and a translinear loop circuit coupled to the input node, the first transistor, and the output driver, the translinear loop circuit comprising, a sinking circuit having a second transistor including a collector, base and emitter, the translinear loop circuit responsive to a sinking current of the sinking circuit and operable to provide a bias current signal proportional to the sinking current, a third transistor having a collector, base and emitter, the collector coupled to the first power supply rail, the base coupled to the input node, a second resistor coupled to the emitter of the third transistor, a fourth transistor having a collector, base and emitter, the collector and base coupled to the second resistor, the emitter coupled to a second power supply rail, a fifth transistor having a collector, base and emitter, the base coupled to the base of the fourth transistor, the emitter coupled to the second power supply rail, the collector coupled to the emitter of the first transistor, a sixth transistor having a collector, base and emitter, the collector coupled to the first power supply rail, the base coupled to the input node, a second current source coupled between the emitter of the sixth transistor and the second power supply rail, the second current source coupled to the sourcing circuit, and wherein the collector of the second transistor of the sinking circuit is coupled to the output node, the base of the second transistor of the sinking circuit is coupled to the second current source, and the emitter of the second transistor of the sinking circuit is coupled to the second power supply rail.
 2. The high efficiency, low crossover distortion, current amplifier circuit as claimed in claim 1, wherein the sourcing circuit includes a seventh transistor having a collector, base and emitter, the collector coupled to the first power supply rail, the base coupled to the first current source, and the emitter coupled to the output node.
 3. A high efficiency, low crossover distortion, current amplifier circuit having an input and output node comprising: a first transistor having a base, an emitter and a collector, the collector coupled to a first power supply rail, the base coupled to the input node; a first resistor coupled to said emitter of said first transistor; a second transistor having a base, an emitter and a collector, the collector and the base of the second transistor coupled to the resistor, said emitter of the second transistor coupled to a circuit a second power supply rail; a first current source coupled to the first power supply rail; a third transistor having a base, an emitter and a collector, the collector and the base of the third transistor coupled to the first current source; a fourth transistor having a base, an emitter and a collector, the collector coupled to the emitter of the third transistor, the base coupled the base of the second transistor, the emitter coupled to the second power supply rail; a fifth transistor having a base, an emitter and a collector, the collector coupled to the first power supply rail, the base coupled the input node; a second current source coupled between the emitter of the fifth transistor and the second power supply rail; a sixth transistor having a base, an emitter and a collector, the collector coupled to the first power supply rail, the base coupled the first current source, the emitter coupled to the output node; a second resistor coupled between the emitter of the third transistor and the output node; and a seventh transistor having a base, an emitter and a collector, the collector coupled to the output node, the base coupled to the second current source, the emitter coupled to the second power supply rail.
 4. The current amplifier circuit as claimed in claim 3 wherein the first, second, third, fourth, fifth, sixth and seventh transistors have the same polarity type.
 5. The current amplifier circuit as claimed in claim 3 wherein the first, second, third, fourth, fifth, sixth and seventh transistors are NPN transistors.
 6. The current amplifier circuit as claimed in claim 3 wherein the first, second, third, fourth, fifth, sixth and seventh transistors are PNP transistors. 